Intel announces detailed process and packaging roadmaps to drive innovation

Intel presented a roadmap of process and packaging innovations to power their next wave of products through 2025, which they said will get back to process performance parity – and then leadership.

Pat Gelsinger, CEO of Intel, at the Intel Accelerated event Monday

On Monday, Intel held a webcast at which they fleshed out their IDM 2.0 strategy initially announced in March, with detailed process and packaging technology roadmaps that extend through 2025. The changes include a complete rebadging of how their process nodes are named, to deal with inconsistencies that are common in the industry, including at Intel. Intel also announced two key new process technologies. RibbonFET is Intel’s first new transistor architecture in more than a decade. PowerVia is a new type of backside power delivery method. Intel also discussed its next-generation extreme ultraviolet lithography (EUV), which it terms High Numerical Aperture (High NA) EUV. They announced forthcoming  Foveros Omni and Foveros Direct packaging innovations. They also gave Intel Foundry Services updates, including their first customer for packaging services, and a major strategic partner, with others hinted to be in the works.

“Today, I want to zoom in on our process and packaging technologies,” said Pat Gelsinger, Intel’s CEO. “We need to accelerate our clock rate of innovation. This will get us to process performance parity – and then leadership – sooner than you think.”

Gelsinger emphasized that the industry’s naming based on traditional nanometer-based process nodes hasn’t actually matched the actual gate-length metric since  1997, so that the ‘nm’ nomenclature is misleading.

“We need to evolve the way we talk about process nodes – the recipes we take for the thousands of steps to build transistors,” he said. “Today we are refreshing our lexicon to create a meaningful framework for customers.”

Gelsinger said that the name of the 10 nm SuperFin will not change since it is already in high production. However, everything after that will change. What Intel has been calling Enhanced SuperFin pending the granting for a formal name will become known as Intel 7. The node after that, which Intel had been calling 7 nm, will become Intel 4. It in turn will be followed by Intel 3, and Intel 20A respectively.

“Intel 7 is the appropriate name for customers to help customers understand the competitive performance being delivered by the node,” said Dr Ann Kelleher, Intel’s senior vice president and general manager of Technology Development. It will deliver an approximately 10% to 15% performance-per-watt increase versus Intel 10nm SuperFin, based on FinFET transistor optimizations.

Dr Ann Kelleher, Intel’s senior vice president and general manager of Technology Development

“This is equivalent to a full node of performance gain,” Kelleher stressed. “Intel 7 realizes this big jump in performance thanks to amazing innovations including moving electrons through the channel faster, by using more low-resistant materials and delivering better energy control through novel, high-density techniques and streamlined structures, enabling improved power delivery, better routing and higher metal stack

Intel 7 products will begin to ship later this year, in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data centre, slated for production in the first quarter of 2022.

“Intel 4 comes after Intel 7, and will be ready for production in the second half of 2022, for product shipping in 2023,” Kelleher said. They include Meteor Lake for client and Granite Rapids for the data centre.

“Intel 4 is also our first node to fully embrace the use of extreme UV lithography, our EUV,” Kelleher said. “EUV involves a highly complex optical system of lenses and mirrors that focuses a 13.5 nm wavelength of light to print incredibly small features on silicon. This is a vast improvement over prior technology that used light at a wavelength of 193 nm.” This comes through Intel’s long-established relationship with ASML.  Intel expects this will translate into approximately a 20% performance-per-watt increase, along with area improvements.

Looking ahead, Kelleher said that Intel will deploy High Numerical Aperture (High NA) EUV, the next generation of this technology.

“High NA will integrate even higher precision lenses and mirrors, improving resolution and allowing even for even smaller features to be printed on the silicon,” she stated. They expect this, the first such tool in the industry, to be in production beginning in 2025.

“Intel 4 will be followed by Intel 3, which will be ready to begin manufacturing products in the second half of 2023,” Kelleher continued. “Our early modelling and test tube data is showing that Intel 3 will deliver around an 18% transistor per watt increase over Intel 4, along with additional improvements in power and area. These amazing results derive from several factors, including the addition of a denser, higher performance library beyond Intel 4, increased intrinsic drive current to fully optimize the FinFET transistor, optimized interconnect metal stack, and increased use of EUV compared to Intel 4. This is a higher level of improvement than a standard full node improvement for us.

Following Intel 4 comes Intel 20A, which throws the naming convention out of whack because it marks the start of the ‘Angstrom Era’ of semiconductors, which is slated for the first half of 2024. An angstrom is the lower unit of measurement under the nanometer, being one-tenth of a nanometer, so if intel had kept the old naming, this would have been Intel 2. The A has been added because it signifies Angstrom.

“Intel 20A will be another watershed moment in process technology,” Kelleher emphasized. “It will feature two ground-breaking technologies – an entirely new transistor architecture named RibbonFET, and a first its kind innovation called PowerVia, to improve power delivery.

Dr. Sanjay Natarajan, Senior VP and co-General Manager at Intel

“I am pumped to take the wraps off two innovations that I believe will continue to transform silicon process technology as we continue to push the boundaries of physics,” said Dr. Sanjay Natarajan, Senior VP and co-General Manager at Intel, who leads the team developing intel’s process technology. “The first is our new Backside Power Delivery Network called PowerVia. This is a unique technology that will make its debut in Intel 20A. Traditional interconnect technology connects on top of the transistor layer. With the resulting intermixing of power and signal wires, routing inefficiencies arise, hampering both processing and power. Our solution is a novel process where the wires are placed underneath the transistor layer on the backside of the wafer. By eliminating the need for power routing on the front side of the wafer, more resources become available to optimize signal routing and reduce delay.”

Natarajan stressed that this allows optimizing for performance, power, and area, depending on the product needs.

“We have been perfecting this process over the past several years, and PowerVia will be the first industry deployment of a back side power network,” he said. He also said Intel will be testing it on earlier nodes before it ramps in volume with Intel 20A in 2024.

Intel 20A will also introduce the first new transistor architecture since FinFET in 2011 – gate all around transistors, which the industry has been working on broadly over the last several years. It wraps the gate completely around the channel for better control and a higher drive current at all voltages, for higher performance, in a smaller footprint than FinFET.

“We call our version RibbonFET,” Natarajan said.

Intel then turned to changes in advanced packaging.

“Packaging is becoming even more important as we now need to scale and stack tiles vertically to realize the effects of Moore’s law,” Kelleher said. “Packaging is also a key component of our IDM 2.0 strategy, enabling us to create leadership products incorporating disparate nodes and processes. She reviewed their EMIB [embedded multi-die interconnect bridge] technology, which has been in production since 2017, and announced Sapphire Rapids will be the first Intel Xeon data centre product to ship in volume with EMIB.

“Sapphire Rapids really is a big deal,” Kelleher said. “It is the first dual-reticle-sized device, delivering nearly the same performance as monolithic designs in the industry. That’s a great achievement, but we have to build it in a cost-effective manner. Sapphire Rapids’ structuring costs will benefit from EMIB’s inherent efficiency of using local silicon interconnect, instead of using a large silicon interposer.” Kelleher also noted they are working on future generations of EMIB, which will scale from a 55-micron bump pitch to 45 microns, and then 40 microns in the third generation.

Foveros leverages wafer-level packaging capabilities to provide a first-of-its-kind 3D stacking solution, and Meteor Lake will be the second-generation implementation of Foveros in a client product. It features a bump pitch of 36 microns, tiles spanning multiple technology nodes and a dynamic thermal design power range from 5 to 125 watts.

Two new technologies, Foveros Omni and Foveros Direct, were then announced.

Dr Babak Sabi, Corporate VP and GM Assembly and Test Technology Development

“We expect Foveros Omni to be ready for volume manufacturing in 2023,” said Dr Babak Sabi, Corporate VP and GM Assembly and Test Technology Development, who leads the team driving roadmap packaging innovations at Intel. “Omni allows integration of multiple disaggregated top tiles with multiple base tiles. Both the top die tiles and base tiles can be mixed across fab nodes. With this flexibility, the design possibilities and performance improvements are literally endless.” The die to die interconnect is a major improvement on the original Foveros, he stressed.

Foveros Direct, which uses solderless direct copper-to-copper bonding, enables lower resistance interconnects, and will also be available in 2023.

“Thie technology will transform heterogeneous integration and truly take packaging technology to the next level,” Sabi said. “We are blurring the lines between where the wafer ends and where packing begins. Foveros Direct enables sub-10-micron bump pitches. This provides an order of magnitude increase in the interconnect density for 3D stacking. This opens up new concepts for functional die partitioning that were previously unachievable. I can’t wait to get these two new packaging breakthroughs into customer hands in 2023.”

Gelsinger then re-emerged to make a pair of announcements around Intel Foundry Services.

“I’m thrilled to announce we have signed AWS as our first customer to use IFS packaging solutions – but there’s more,’ Gelsinger said. “I’m also excited about the opportunity to partner with Qualcomm using our Intel 20A process technology.

“IFS is off to the races,” he emphasized.

Subsequently, in taking media questions, Gelsinger indicated that while AWS and Qualcomm are the only two companies in this ecosystem they are prepared to name now, they are talking to others, some of whom would have been considered competitors in the past.

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